Cadence® Sigrity™ XcitePI™ Extraction technology takes chip layout data in GDSII or LEF/DEF formats, and generates a comprehensive SPICE model that consists of a fully distributed PDN and I/O nets and solvers for all electromagnetic (EM) coupling effects between signals, power, and ground. The models can be used in conjunction with models of package and boards for chip/package/board power-integrity (PI) or power-aware signal-integrity (SI) analysis.
XcitePI Extraction facilitates effective design with a range of electrical performance assessment and visualization options. These options show the impact of changes to capacitor locations, bump, pad, and power grid designs, helping design teams avoid costly late-stage design re-spins.
➤ Maximum accuracy with a compact chip model that is spatially distributed with high pin resolution